Im working on a lab where I need to design a simple CPU using a TOY ISA in Logisim. Ive completed the instruction fetch and decode stages, but Im struggling with designing the control unit to correctly generate signals for each opcode. Im also unsure how to properly connect the ALU operations with the register file and control signals. Specifically, I need help mapping opcodes to control outputs (like load, store, reg write, etc.) and verifying that the data flows correctly through the CPU.
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