Request for Digital Logic Design Project (8-to-1 Multiplexer…

I am looking for someone to complete a Digital Logic Design project for me from start to finish. The project must be done using Quartus Prime Lite Edition and simulated via Questa/ModelSim.

Project Requirements:

1. Design Task: Build an 8-to-1 Multiplexer using a Hierarchical approach (connecting multiple 2-to-1 Mux units using AND, OR, and NOT gates).
2. Schematic Capture: A complete .bdf file showing the gate-level circuit.
3. VHDL Coding: A separate .vhd file with the VHDL description of the hierarchical design.
4. Simulation: Functional simulation and Timing Diagrams to prove the design works correctly.

Deliverables:

• Video 1: Explanation of the Schematic design and its simulation results.
• Video 2: Explanation of the VHDL code and its simulation results.
• Both videos must show the Timing Diagram and include a clear voice explanation of how the circuit functions.

Please let me know if you can handle this and what your timeline and terms are.

Best regards,

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